The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-152

“VLSI Design of Adaptive Neural Systems”

by Bang Won Lee

May 1990

VLSI neural circuits play an important role in exploring and exploiting the rich properties of neural networks associated with massively parallel processing using analog neurons and synapses. The algorithms for artificial neural networks can be mapped to the VLSI neural systems if the building block exist. Novel techniques which find and eliminate the local minima in Hopfield networks have been developed. With modified Hopfield networks using these techniques, the local minima in Hopfield neural-based A/D converters and traveling salesman problems are successfully eliminated. A competitive Hopfield network, is very effective and efficient in finding a valid, near-optimal solution for the combinatorial optimization problem. The hardware annealing technique using the analogy between the annealing temperature and neuron gain is also described. Due to intrinsic continuity of the hardware annealing process, the computational time for searching the optimal solution is minimized. A compact and electrically programmable analog synapse cell in CMOS technologies is presented. Both DRAM-style and EEPROM-style weight storage mechanism are explored. By using the programmable synapses and gain-adjustable neurons, prototyping integrated-circuits which can operate in either asynchronous or synchronous modes are fabricated and evaluated. The neural-based A/D conversion and digital image restoration are used as system-level application examples. The VLSI neural chips can conduct network retrieving and learning processes concurrently. In the DRAM-style neural chips, weights of analog synapse cells are externally programmed and require dynamic refreshing. In the EEPROM-style neural chips, synapse weights are permanently stored in the floating gate. If the compact synapse and neuron cells are used in the industrial-level 1-mm VLSI technologies, a fully-connected general-purpose neural chip with 500 neurons can be achieved in 1 silicon area.

To download the report in PDF format click here: USC-SIPI-152.pdf (6.7Mb)