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“Design and Reliability Simulation of VLSI Computing Circuits”
by Wen-Jay Hsu
August 1991
Design of very large-scale integration (VLSI) computing circuits require good means to assess circuit reliability in order to utilize the full potential of advanced submicron fabrication technologies. An integrated circuit may fail due to the degradation of some critical transistors or interconnection wires. This dissertation presents the integration of reliability modeling into the developed circuit simulator, RELY, which can predict circuit performance degradation due to progressive physical failure mechanisms. Modeling requirements and implementation of hot-carrier effects and electromigration including transistor modeling, stress monitors and degradation models for reliability simulation are addressed. Two simulation schemes for circuit reliability analysis are presented. Quick identification of weakest devices within a circuit can be achieved by the one-cycle simulation scheme. The repetitive simulation scheme provides the information on the impact of the progressive device degradation on circuit performance to account for the gradually changing stress condition in actual circuit operation. A systematic approach to include the first-order AC degradation effects in the quasi-static simulation is also described. Strategies for use in a hierarchical reliability simulation environment covering various levels of VLSI circuit design are presented. The degradation information is propagated through the design hierarchy starting from the circuit-cell level, the circuit-block level to the complete chip level. Reliability simulation using the RELY program can not only predict the degraded performance of the whole circuit, but also identify the most critical devices for improvement. Circuit topology changes can be applied to achieve high failure-tolerance in the computing circuits. Design examples of computing circuits and the associated performance degradation are presented. Example circuits including inverters, NAND gates, memory circuits, operational amplifiers and data converters have been studied using the industrial 0.8 mm and 0.5 mm CMOS technologies. By using these techniques on the design of CMOS components, high-speed circuits can be achieved with excellent long-term reliability. By adding a common-gate buffering transistor in the critical output stage of an operational amplifier, circuit lifetime is found to be improved by more than four times.