The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-189

“Automated Synthesis of Analog MOS VLSI Circuit Modules”

by David Jan-Chia Chen

December 1991

Recent advances in VLSI technologies have allowed the integration of information processing subsystems on one chip, including both analog and digital parts. In addition to the conventional telecommunications and computer networking applications, new applications of mixed analog-digital VLSI are being unveiled in the fields of image processing and neural-based flexible information processing. The need for computer-aided design tools to reduce the dominant analog circuit design time and cost for such processor chips has become imminent. This thesis presents advanced methods for automatic synthesis of analog MOS VLSI circuit modules. A design system that consists of a knowledge-based synthesis tool and a constraint-based layout generator has been developed to automate the design of key analog MOS circuit modules. An expert system has been developed to assist in an iterative analog design process. This integrated-circuit design expert system, which interfaces with a circuit simulator, is capable of optimizing circuit topologies as well as circuit element geometries to better satisfy a given set of performance specifications. The constraint-based layout generator uses analog circuit recognition and critical-net analysis techniques to identify crucial portions of an analog circuit and systematically derive proper layout constraints for analog circuit performance optimization. Constraint-driven floorplanning and routing techniques are developed to generate high-quality full-custom analog circuit layouts which incorporate the layout constraints. This layout tool is capable of quickly generating a correct and high-performance custom layout with a selectable aspect ratio for a wide variety of analog circuit modules. Extensions to higher-level subsystem layout synthesis using hierarchical floorplanning and module generation techniques are also described. Automatic layout generation techniques for single- and multi-layer neural networks have been developed. Experimental results on several CMOS Op-Amps, a voltage comparator, and a 16-neuron Hopfield neural network are described. These results indicate that this new analog circuit synthesis approach provides two advantages: it is quite general and yet effective, and can be used by system designers who are inexperienced in analog circuit design.

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