The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-194

“VLSI Programmable Processor Design”

by Bing J. Sheu and Min Chen

January 1992

By combining the technologies of Complementary Pass-Transistor Logic (CPL) and CMOS Logic, the response time of the 32-bit carry lookahead adder can be reduced to 2.35 ns. At the same time, the constant height can be maintained under 200 l.

To download the report in PDF format click here: USC-SIPI-194.pdf (14.5Mb)