The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-203

“VLSI Image Compression”

by Wai-Chi Fang

May 1992

The increasing demands of speed and performance in data compression applications urge the VLSI data compression research. Our VLSI data compression research has been inspired by the neural networks, the parallel/pipelined processing, and the VLSI technologies. The primary objective was to develop effective image compression algorithms and their associated VLSI processors. The scope of our VLSI image compression research covers: (a) lossless image compression and VLSI processors, (b) lossy image compression and VLSI processors, and (c) neural network based image compression and VLSI neuroprocessors. The significant research results are presented in the following:

A systolic array architecture and the associated VLSI processor for the binary tree-searched vector quantization has been developed to achieve high speed lossy image compression. A 16-dimension 8-level tree-searched difference-codebook vector quantizer prototype chip was designed onto a 8.7 x 7.7 mm2 chip in a 1-mm technology. The vector quantizer throughput rate is 20 Mpixels per second.

A high-speed VLSI neuroprocessor for adaptive image compression based upon a frequency-sensitive self-organization algorithm (FSO) has been developed. Performances of the FSO neuroprocessor can achieve near-optimal results and a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog programmable synapses and neurons to perform parallel computation and digital circuitry to handle digital codebook training was used. A 25-dimension 64-codevector vector quantizer prototype chip was designed, fabricated, and tested. It provides an intrinsic computing capability as high as 3.2 billion connections per second.

A neural network based optical flow processor has been developed to achieve a high-speed long-range motion detection for efficient video motion compression. An extendible VLSI neuroprocessor has been designed with a silicon area of 2,482 x 5,636 l2 in MOSIS scalable CMOS process. A 1.25 x 1.17 cm2 chip in a submicron CMOS technology can accommodate 128 velocity-selective neuroprocessors and achieve 166.4 Giga connections per second.

A high-speed VLSI pipelined processor design for the effective lossless compression based on an advanced Rice algorithm PSI14,K+ has been developed. The chip occupies a compact chip area of 5.1 x 5.3 mm2 in a 1.0-mm CMOS technology and operates up to 40 Mpixels/sec.

To download the report in PDF format click here: USC-SIPI-203.pdf (9.8Mb)