The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-209

“An Analog Edge Detection Chip and A Digital Neural Multiprocessor Chip for Machine Vision Processing”

by Hiroto Okada

June 1992

A combination of an analog front-end chip and a digital neural multiprocessor array chip can play an important role in exploring and exploiting vision processing which demands tremendous parallel communications and computations. The analog front-end chip which integrates a photosensor array and pre-processing elements, and performs edge detection on an image captured in the photosensor array is presented. The nature of analog processing obtained in the analog edge detection chip can provide high parallelism for the whole system, eliminating sequential procedure caused by A/D conversion which is required in a digital processor. The photosensor are realized using parasitic bipolar transistors in a digital CMOS process. The edge detection are done by convolution using the 3 x 3 Laplacian operator. The edge detection chip consisting 50 x 66 cells can be implemented in a chip of 7.9 mm x 9.2 mm, using the MOSIS 2.0-mm CMOS p-well technology. A digital multiprocessor array chip is also described. The digital multiprocessor array chip can construct 1-dimensional ring-connected systolic and 2-dimensional mesh-connected systolic array, which can effectively perform representative neural network algorithms such as the back-propagation network, and competitive learning. A systolic array, where communication and computation are well balanced, is a suitable architecture for neurocomputer because its features such as regularity and modularity are desirable for VLSI implementation. The digital multiprocessor array chip includes four-bidirectional buses connecting the four nearest cells and 256 words of 8-bit data cache for supporting the systolic array operation. Twenty processing elements have been implemented in an 19.3 mm x 20.9 mm chip, using the 0.5-mm CMOS technology provided by TRW, Inc. and achieve 2 billion connection updates per second.

To download the report in PDF format click here: USC-SIPI-209.pdf (2.8Mb)