The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-225

“BSIM_plus: An Advanced MOS Transistor Model for VLSI Circuis”

by Sudhir M. A. M. Gowda

November 1992

The BSIM_plus MOS transistor model is developed for design and simulation of analog and digital very large-scale integration (VLSI) circuits in sub-half-micron technologies for advanced signal processing, parallel computing, and telecommunication applications. A compact parameter set is created to characterize transistors and achieve continuity of the drain current and its derivatives. Advanced transistor modeling techniques are used for critical quantities including the threshold voltage and carrier mobility. Effects of non-uniform substrate doping and drain-induced barrier lowering are included in the threshold voltage expression, along with narrow-channel effects. Mobility reduction due to the transverse and lateral electric fields is also included. This model includes consistent charge and capacitance expressions that achieve charge conservation an high accuracy. A built-in substrate current expression serves the purposes of predicting circuit performance and reliability. Temperature and noise effects are included. The pseudo-boundary method is used to extend the use of a parameter set over the whole design space. This improves simulation results for circuits using large transistors such as digital drivers and analog voltage references, as well as for the prediction of circuit performance using next-generation technologies.

The BSIM_plus model is implemented in a modified version of the SPICE-3 circuit simulator from University of California, Berkeley. Parameter values can be extracted using a modified version of the SUXES extraction program from Stanford University. Simulation results agree well with measurement data of transistors from sub-half-micron technologies of TRW Inc. and Samsung Electronics Co. Simulation results of VLSI circuits including self-timed adder, asynchronous master-slave latch, memory circuitry and operational amplifiers are presented. The required computing time and convergence properties of the simulation are compared by using the BSIM_plus model and various built-in MOS models in the SPICE circuit simulator. The convergence property of this is greatly enhanced due to the improved smoothness of the device characteristics. The BSIM_plus model functions as the cornerstone of an integrated simulation environment for advanced VLSI circuits.

To download the report in PDF format click here: USC-SIPI-225.pdf (6.4Mb)