The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-246

“Analog-Digital VLSI Neuroprocessors for Signal Processing and Communication”

by Joongho Choi

December 1993

Advances of computing systems and communication networks have made it possible to integrate the distributed information from a wide range of data fields. Integrated information processing systems process various data such as the image, voice, and text in order to support multi-media applications. High performance computation of data processing algorithms in real-time applications is indispensable for achieving these systems. The artificial neural network approach is one very promising method to enhance computational capabilities with rapid progresses of VLSI technologies. In order to take advantage of the fully massive parallelism of neural network computing, computations should be efficiently realized in hardware-software codesign with a neurocomputer or neuroprocessors. The analog neural computing approach with the assistance of digital control signals provides efficient implementations of high-performance artificial neural network processors with optimization on the operation speed, silicon area, and power consumption. Based upon this design methodology, key building blocks such as synapse cells and neuron cells are designed. With an industrial-level submicron VLSI technology, a fully-connected general-purpose neural chip can perform more than 30 giga-connections-per-second (GCPS). A neuroprocessor for self-organization mapping has been fabricated and evaluated, which is aimed for pattern recognition, data compression, and other signal processing applications. The high-precision winner-take-all circuit, which is a key element of the competitive learning, is designed with performance-improving techniques such as cascading, distributed biasing, and dynamic current steering. An application-specific neuroprocessor chip has also been developed for the receiver in wireless communication. It is based on a four-layered neural network. System-level analysis and evaluation have been conducted. The accomplished research has paved an important foundation toward the construction of full-scale engineering neural systems in compact electronic hardware for scientific and biomedical applications.

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