#### Technical Report USC-SIPI-258

“Optoelectronic Sorting Networks”

by Yibin Lu

March 1994

This dissertation presents an optoelectronic implementation of multistage sorting networks. Volume (3-D) sorting networks which utilize the high spatial bandwidth and parallelism of optics are discussed. Designs for the diffractive optical elements (DOEs) used for the interconnections and optoelectronic compare-and-exchange (C&E) modules used for the dynamic sorting nodes are given.

The first part of this work describes the network properties of various conventional 2-D sorting networks and the development of their corresponding 3-D structures. A merge procedure is proposed for network expansion in 3-D space. The mathematical framework and detailed analysis are given. The decision of choosing a specific network structure depends on two factors: the cost of optical elements and switching elements; and the complexity and reliability of the network.

Designs of optical interconnection systems for one-to-one linear mappings and 2-D folded shuffles are presented in the second part of this work. Our study of the characteristics of Gaussian microbeams propagating in microscaled diffractive optical elements provides a useful method for analyzing the packing limitations and light efficiency of each network structure. In our work, short and long distance linear mapping interconnections are accomplished by using microlens arrays. Various approaches are proposed to implement 2-D folded shuffles. Phase-only blazed gratings and off-axis microlenses are used for space-variant designs, and a demagnifying algorithm is proposed for space-semivariant designs. Mathematically modeled error functions are developed for performance analysis.

The last part of this dissertation describes systematic design methods for the optoelectronic 2 input/ 2 output multifunctional C&E modules. We choose smart pixel optoelectronic devices having both optical and electronic functionality for implementing the logic functions. The particular device technologies used are L-SEEDs, FET-SEEDs, and OEICs. We consider the packing density limitations due to three main factors: optical diffraction, pixel size, and power dissipation. Based on state-of-the-art technology, the analysis shows that the power dissipation of the smart pixel devices currently limits the number of modules that can be integrated in a single chip.

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