The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-282

“Compact VLSI Array Processors Design for Multimedia Applications”

by Robert Chen-Hao Chang

April 1995

With rapid advances of deep-submicron microelectronic technologies, a high-performance intelligent system with tens of millions of transistors can be integrated onto a single chip. The compact, high-computing power systems become feasible with significant progresses in the research and development of advanced computing architecture and array processing. Extensive studies of artificial and biological neural networks, which have inherent massively paralleled and distributed signal processing capabilities, have provided an excellent means to perform several complex functions in scientific and engineering applications such as image/pattern recognition, medical image, computer vision, path planning, and autonomous robots. Array processors based on cellular neural networks combine some features of fully interconnected neural networks with the nearest neighbor interactions and are especially well suited for very large-scale integration (VLSI) implementation. A 5 x 5 paralleled array processor chip has been designed and fabricated by using the 2-_m CMOS technology from the MOSIS Service. The prototype chip with digitally-programmable weights was constructed with many compact mixed-signal VLSI circuit components which were designed using the current-mode techniques. The low-voltage, low-power operation is supported with the current-mode scheme which scales well with the supply voltage. Measurement results of the VLSI computing cells are presented. Experimental results obtained from a custom-made circuit board are provided to illustrate the operation of the prototype chip. The software-hardware codesign methodology is used to implement the high-performance intelligent microsystem which can be constructed by the array processor chips and software program. Neural networks with the hardware annealing method are very energy-efficient in solving many complex optimization problems. Demonstration of novel operation to achieve optimal solution at fast signal processing using standard IC parts is given. VLSI design of a variable-gain neuron circuit can be incorporated into the prototype chip to realize the optimal solution capability.

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