The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-298

“Optoelectronic Cellular Array Processor with Reduced Cellular Hypercube Interconnections”

by Jeng-Feng Lin

May 1996

This work describes several optoelectronic interconnection techniques that reduce the communication latency of large single-instruction-multiple-data (SIMD) mesh-connected cellular array processors. These methods combine the local interconnection advantages of electronics with the longer distance interconnection advantages of optics. This work describes several classes of reduced cellular hypercube (RCH) optoelectronic interconnections, which improve on previous cellular hypercube (CH) interconnections by discarding some short distance links, making multiplexing more efficient and relieving certain types of contention. A potentially optimal control algorithm and dedicated hardware design for the optical time multiplexing system are also given. For a mesh-connected array, the network diameter is reduced by a factor of 5.5 and the inter-processor communication is accelerated by a factor of 5 for some common operations, if the RCH interconnections are combined with the mesh. Other multiplexing schemes are also presented in addition to the time multiplexing scheme. To design the computer-generated grating needed for optical implementation of the RCH interconnection pattern, this work introduces a two-stage iterative Fourier transform algorithm, which incorporates an optimization of the intensity ratio of the minimum signal order to the maximum noise order (SNRmin). Numerical results show that this algorithm can significantly increase SNRmin with only a slight deterioration in uniformity and diffraction efficiency. A promising way to build the optoelectronic cellular array processor is to implement the whole PE array in one or a few CMOS chips integrated with detectors and vertical-cavity surface-emitting lasers. The potential performance of this optoelectronic cellular processor versus purely electronic CMOS technology is estimated as a function of power dissipation and other physical parameters. The estimates include models for the electronic processing circuits, optical receiver, and optical transmitter in the cellular array under the assumptions of CMOS technology and feature sizes from 0.8 to 0.15 mm.

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