The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-302

“VLSI Array Sensory Information Processing for Communication and Multimedia”

by Eric Ying-Chin Chou

December 1996

As multimedia applications emerge as an important driving force for the integration of microelectronic systems for computing, communication, and signal processing, powerful front-end information processing at the sensor part becomes increasingly important to enhance the precision and processing bandwidth of communication receivers or signal acquisition devices. Monolithic realization of robust real-time sensory processors is specially desired to handle in-coming signal sequence to more informative or compressed format. Mixed-signal very large scale integration (VLSI) microsystems design is an extremely effective enabling technology for the array sensors when data throughput, silicon area, and power consumption are considered.

In order to resolve the challenging situation of co-existence of the circuit behavior and the algorithmic function of a smart VLSI sensor, an architecture-driven design approach is suitable for the concurrent development in algorithmic level and circuit level while maintaining design integrity. State-constrained neuron model is a mathematical neuron model which eliminates the out-of-bound problem and ensures the stability in solving combinatorial optimization problems. Compact neural network is a scalable VLSI massively parallel processing architecture consisting of state-constrained neurons.

With collective computation and programmable data routing, a two-way multiplexing and pipelined VLSI architecture has been invented to fully exploit the parallelism of the input data stream. Array sensory processors have been successfully implemented for a combinatorial optimization chip, a VLSI detector chip for partial response signaling, and a VLSI connected component detector chip for early computer vision. Algorithmic studies on wireless communication receiver design and signal processing machine design were also performed. The current-mode CMOS VLSI implementation for partial response maximum likelihood (PRML) detector chip have been designed to achieve a detection rate of 53 Mb/s for class IV partial response signaling with a 20-neuron processing engine in a 2.3 x 2.6 mm2 die in a 1.2 _m high performance CMOS technology through the MOSIS Service, of USC/Information Sciences Institute in Marina Del Rey, California.

To download the report in PDF format click here: USC-SIPI-302.pdf (33.8Mb)