The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-321

“A Deep Submicron Drain-Current and Charge Model for MOS Transistors”

by Hung-Min Jen

August 1998

The unified short-channel MOS (S-CMOS) transistor model has been developed for design and simulation of deep-submicron low-voltage mixed-signal very large-scale integration (VLSI) circuits for high-speed computing, high-frequency communication, and multimedia applications. Unified expressions for drain current, conductances, terminal charge, and capacitances are derived with the assistance of three smooth functions including hyperbola, exponential interpolation, and sigmoid functions, which provide the excellent transitions between different regions of operation. A compact parameter set of 35 parameters is created to characterize transistors. Effects of non-uniform substrate doping, drain-induced barrier lowering, narrow-channel and reverse short-channel are included in the threshold voltage expression. The mobility reduction due to the lateral and vertical electrical fields is modeled by including the second-order term to provide a higher accuracy for deep-submicron transistors. The output conductance in saturation region is accurately modeled by the expression for channel-length modulation effect. The charge/capacitance model uses an accurate formulation for back gate degradation coefficient to model the channel charge density. The unified expressions of charge densities are derived valid for all operation regions including the accumulation region. Different channel-charge partitioning schemes, including 40/60, 0/100, and 50/50, are provided to have better usage of the model in different applications. The parameter extraction of S-CMOS model is based on the physics characteristics of each parameter in the model and implemented by using MATLAB program. Both the local determination and global optimization strategies are combined to increase the extraction accuracy and reduce the computation time. The S-CMOS model is implemented in a modified version of the SPICE-3 circuit simulator from University of California, Berkeley. Simulation results of mixed-signal circuits including domino logic gate, folded-cascode operational amplifier, analog comparator, wide-range Gilbert multiplier, and DRAM circuit are presented. Comparison of simulated results and measured data of transistors demonstrate the accuracy of the S-CMOS model and its strong capability in the deep-submicron technologies. In the appendix, research work on modeling MOS transistors for use up to 10 GHz is described with careful comparison of measured and simulation results.

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