The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-323

“Integration of Optpelectronic Technologies for Chip- to-Chip Interconnections and Parallel Pipeline Processing”

by Jen-Ming Wu

December 1998

Digital information services such as multimedia systems and data communications require the processing and transfer of a tremendous amount of data. These data need to be stored, accessed and delivered efficiently and reliably at high speed for various user applications. This represents a great challenge for current electronic systems. Electronics is effective in providing high performance processing and computation, but its input/output (I/O) bandwidth is unable to scale with its processing power. The signal I/Os or interconnections are needed between processors and input devices, between processors for multiprocessor systems, and between processors and storage devices. Novel chip-to-chip interconnect technologies are needed to meet this challenge. This work integrates optoelectronic technologies for chip-to-chip interconnects and parallel pipeline processing. Photonic and electronic technologies are complementary to each other in the sense that electronics is more suitable for high-speed, low cost computation, and photonics is more suitable for high-bandwidth information transmission. Smart pixel technology uses electronics for logic switching and optics for chip-to-chip interconnects, thus combining the abilities of photonics and electronics nicely. This work describes both vertical and horizontal integration of smart pixel technologies for chip-to- chip optical interconnects and its applications. We present smart pixel VLSI designs in both hybrid CMOS/MQW smart pixel and monolithic GaAs smart pixel technologies. We use the CMOS/MQW technology for smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing. We have tested the chip and constructed a prototype system for device characterization and system demonstration. We have verified the functionality of the system and characterized the electrical functions of the chip and the optoelectronic properties of the MQW devices. We have developed algorithms that utilize SPARCL for various image processing applications. We demonstrate the SPARCL system for digital image edge detection and digital video motion estimation. We also present the design of a monolithic integrated GaAs smart pixel array for network interface (SAPIENT) and the development of a smart ADD/DROP protocol in its design. Smart pixel systems require micro diffractive optical elements, and we have investigated their use for beam focusing and steering applications. Most diffractive optical elements are designed based on scalar diffraction theory. We have analyzed this design procedure and quantified the design error due to evanescent diffraction and other sources. We also present a novel design for diffractive microlenses that uses hybrid multiple phase levels. With this method, the diffraction efficiency of diffractive microlenses is improved at higher numerical aperture. The design, analysis, and experimental test of experimental diffractive microlenses is presented. We also present an architectural analysis of optoelectronic VLSI systems for SIMD parallel processing. We develop system architectures that benefit from chip-to-chip optical interconnects. We discuss the I/O bottleneck problem of conventional SIMD systems and show how parallel pipeline optically interconnected architectures with instruction pipeline design can alleviate the problem. In particular, we compare conventional SIMD system with SPARCL systems that use either 1-D electrical input/outputs (I/Os) or 2-D optical I/Os between the PE array and external devices.


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