The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-352

“High-Frequency Mixed-Signal Silicon-on-Insulator Circuit Designs for Optical Interconnections and Communications”

by Liping Zhang

May 2002

This research explores architectures and design principles for monolithic optoelectronic integrated circuits (OEICs) through the design and implementation of a.) a parallel-pipelined media networking and signal processing network; and b.) low-power radio-frequency mixed-signal complementary metal-oxide semiconductor (CMOS) silicon-on-insulator (SOI) circuit and chip designs for wireless and optical communications fabricated in Ultra-Thin Silicon-on-Sapphire (UTSi_-SOS) technology.

A signal processing and networking platform called reconfigurable translucent smart pixel array (R-TRANSPAR) has been implemented. The system uses interlaced 2D arrays of vertical-cavity surface-emitting lasers (VCSELs) and metal-semiconductor-metal (MSM) detectors provided by Honeywell for optical interconnections. The detected optical current is converted into voltage and amplified for further single-instruction multiple data (SIMD) parallel pipeline signal processing and networking. Both free-space and image-fiber chip-to-chip optical communications have been demonstrated based on this platform. A novel 3D optical parallel data packet (OPDP) switching multi-token-ring network has been designed, implemented and demonstrated. Time-division multiplexed (TDM) network node addressing technique is used to enhance channel utilization and throughput.

The ultimate goal of this research is to integrate monolithically silicon CMOS with optical devices for high capacity media processing and communications. High throughput interconnections demand low noise, high gain-bandwidth product transceivers. We have identified that ultra-thin silicon-on-sapphire as the most promising CMOS SOI technology because of its optically transparent, electrically full-insulating sapphire substrate. The matched thermal expansion coefficients of sapphire with GaAs semiconductor optical devices are desirable for flip-chip bonding.

Four mixed-signal chips have been designed and fabricated in 0.5 _m CMOS SOS technology through MOSIS. Two 2000 CMOS SOS smart-pixel array chips were designed for wire bonding and two recent SOS chips are designed to be flip-chip bonded with VCSELs and photodetectors arrays. Novel monolithic PIN optical detector arrays have been designed and fabricated in UTSi-SOS technology. Various low-power and high frequency techniques including dynamic threshold voltage have been explored. Monolithic multi-GHz _/4 quadrature phase voltage-controlled oscillators (VCOs), radio frequency (RF) transceivers arrays with built-in self-test (BIST) circuits, full monolithic photoreceivers, differential VCOs, mixers, baluns, and phase-locked loop based clock data recovery circuits have been designed and fabricated in CMOS SOS technology for wireless, optical interconnections and communications.

To download the report in PDF format click here: USC-SIPI-352.pdf (42.8Mb)