The USC Andrew and Erna Viterbi School of Engineering USC Signal and Image Processing Institute USC Ming Hsieh Department of Electrical Engineering University of Southern California

Technical Report USC-SIPI-378

“Power Efficient Applications on Embedded Systems”

by Yu Hu

December 2006

This dissertation proposes a complete solution for power efficient multimedia applications on embedded system. We concentrate the research on the emerging video standard: H.264/AVC, both in the encoder and decoder ends. First a run-time power/energy estimation model is presented to provide a fast yet accurate tool for the energy analysis of multimedia application on embedded system. Then a rate-distortion-complexity (RDC) optimization algorithm is proposed to simplify the H.264/AVC motion estimation, which is the most energy-consuming component in this emerging video standard. Based on this RDC framework, a fast inter mode decision algorithm is used to enhance the energy saving. Finally a decoder-friendly adaptive de-blocking filter (DF-ADF) mode decision algorithm is proposed to reduce the decoder energy consumption requirement.The power dissipation of a wide spectrum multimedia applications on VLIW processor is studies first to characterize their power performance. As revealed by collected statistics, the instruction decode unit in a VLIW processor consumes nearly 50% of the total energy in most multimedia applications. This implies that the instruction set architecture (ISA) design is the key to the power minimization of an embedded multimedia system. The power profiling result suggests a strong correlation between IPC and power dissipation. By exploiting this relationship, the power and the energy models for multimedia applications in VLIW processors were proposed. The proposed model was validated by the TI C6416 chip-set, yielding a low error rate. This simple model leads to efficient run-time power estimation for various multimedia systems, and provides insights into the energy saving of the VLIW processor.It is observed that motion estimation is the most complexity- and energy-expensive component in H.264/AVC Therefore a novel complexity adaptive motion estimation was proposed and applied to the H.264 video standard so that the encoder motion estimation complexity is reduced with little degradation in video quality at the price of small bit rate increase. Experiments were conducted using test sequences with low to high motion activities to demonstrate the advantages of our proposed system. Up to 35% motion estimation complexity can be saved at the encoder with less than 0.2 dB PSNR loss and a maximum increase of 3% bit rate.To further improve the complexity saving, a complexity-constrained inter-mode decision algorithm for H.264/AVC video coding was developed. The proposed algorithm, i.e., the ''mode skip test", is followed by the rate-distortion-complexity (RDC) optimization framework. To be more specific, the ``mode skip test" is executed between the MV search for mode 16x16 and that for mode 8x8. It contains two tests to check the number of DCT coefficients of prediction errors quantized to zeros and use it to predict whether the underlying block modes can be skipped or not. As a result, more redundant block modes can be filtered out to save the complexity while maintaining the excellent coding performance of H.264/AVC. The corresponding energy saving shows the similar trend as the complexity saving.A novel decoder friendly adaptive deblocking filter (DF-ADF) mode decision algorithm was examined. Both the complexity and the energy saving of the decoder relys on the usage of ADFs. We first construct the complexity model for the deblocking filter, and the energy consumption model is built based on the IPC-based dynamic power model described in Chapter 3. Then, the encoder performs the rate-distortion-decoder complexity (RDC) optimization to save the energy needed for deblocking filter operations in decoding. We observed a significant amount of energy saving (up to 30%) in the deblocking filter with negligible quality degradation (less than 0.2 dB) and bit rate raise (within 1%).

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