Free Space Digital Optics Research
We study the use of free space optical interconnections within VLSI circuitry to create new computing and networking architectures that are characterized by very high aggregate throughput data I/O ( > 1 terabit/second). We consider the system implications of eliminating the chip I/O bottleneck by creating optical off-chip connections very high in number (30,000/cm2) and operating at on-chip clock rates.
Shown here is a system concept showing four smart pixel stages in a system that performs parallel pipelined cellular logic processing. Green lines show electronic control signals to each stage and red lines show the 2-D optical interconnect channels between stages.
Smart Pixel Systems
Smart pixel systems use VLSI chips containing two dimensional arrays of circuits each contain optoelectronic devices that detect and transmit digital optical signals. This technology allows VLSI chips to receive and transmit data in two-dimensional parallel format. Data flows directly between the core circuitry of interconnected chips, bypass traditional method using perimeter wire-bonds, package and printed circuit board traces. The optical channels are free from off-chip parasitics and crosstalk problems that limit electronic channel rates and density. Below is a list of smart pixel systems we have developed in our lab.
Translucent Smart Pixel Array (TRANSPAR)
TRANSPAR is our latest concept. The TRANSPAR architecture is optimized for two functions: 1.) network interface for 3-D data packet transfer between computing nodes using a carrier-sense-multiple access/collision detection (CSMA/CD) protocol; and 2.) high-throughput SIMD-type processing of 2-D data fields.
Smart Pixel Network Interface (SAPIENT)
SAPIENT interfaces a computing node to a optical packet-based network. Packet are encoded as a two-dimensional field that passes in parallel through the network, occupiying each node for only a single clock cycle. We currently have a laboratory demonstration of based on M.I.T.s OPTOCHIP technology. This technology integrates OPFET detectors and LED transmitters monolithically in standard GaAs circuitry.
Smart Pixel Array Cellular Logic Processor (SPARCL)
The SPARCL system is a 2-D parallel pipeline architecture (shown above). This system passes 2-D fields of data between stages that perform cellular logic processing. Our laboratory system demonstrates examples of pipelined image and video processing. Our system uses chips fabricated at Lucent Technlogies through their OE/VLSI technology.
FET-SEED smart pixels
In early work with smart pixels, we designed smart pixels to perfrom switching and memory functions in a multi-stage interconnection network.
Diffractive Optical Elements (DOE)
One of the critical components for future success of free-space digital optics systems is packaging. We design Diffractive Optical Element (DOE) microlens arrays that create 2-D arrays of optical "micro-channels" between smart pixel arrays. This technology offers compact, rugged optical systems that are scalable in a cost effective manner.
Cellular Hypercube Interconnections
DOEs or other holographic methods can be used to create an interconnection topology for a smart pixel processor. One topology in particular, the cellular hypercube, can greatly enhance the mesh topology commonly found in processor arrays.
Contact Charles Kuznia about webpage, last updated April 27, 1998.