The SPARCL chip was implemented using the CMOS/MQW optoelectronic technology developed at Bell Labs, Lucent Technologies. This technology flip-chip bonds GaAs/AlGaAs multiple-quantum-well (MQW) diode arrays onto CMOS circuitry fabricated through a standard CMOS foundry. The VLSI circuitry connects to the MQW diodes and uses them as optical detectors, modulators or light-emitting diodes to create free space optical I/O ports. MQW arrays of density 28,000 SEED/cm2 has been successfully flip-chip bonded onto Hewlett-Packard's standard 0.5 micron process to create a 256 input - 256 output ATM switch chip with more than 4000 optical inputs/outputs operating at 200 Mbits/ [see OEVLSI web page]. We have measured the MQW modulation characteristics. Click here for results and a description of our optical links.
A system schematic of the Smart Pixel ARray Cellular Logic (SPARCL) system. The SPARCL performs parallel pipeline operations on two-dimensional data fields. The red lines represent optical free space digital channels between processing stages. Each channel operates at on-chip clock rates to create high data throughput. The green lines represent electrical signal lines used for instruction, clock, and data loading/unloading operations.
| This photo shows the SPARCL chip before the MQW flip-chip bonding process. The SPARCL contains a 5 x 10 array of mesh connected smart pixel processing elements (indicated by the white circles). Data in electronic form enters from the left and exits on the right. Data in optical form enters and exits the smart pixels directly. | |
This 2 x 2 mm2 CMOS chip contains an array of 200 flip-chip-bonded MQW diodes in the form of a 20 x 10 array. The diodes have optical windows of 18 microns square and are placed on a 62.5 x 125 micron pitch, covering an area of 1.25 x 1.25 mm2. The diodes have optical windows of 18 microns square and are placed on a 62.5 x 125 micron pitch, covering an area of 1.25 x 1.25 mm2.
We used the core 1.25 x 1.25 mm2 of the chip to implement a 5 x 10 array of smart pixel processing elements, each of size 250 x 125 micron square. Accordingly, each SPARCL chip has the capability to process 50 data elements in parallel. Figure 2 is a photo of the SPARCL chip before flip-chip bonding of the MQW diodes. Overlaid on the photo is a 5 x 10 array of circles indicating the center of each smart pixel. On the perimeter of the 5 x 10 smart pixel array are memory elements (indicated by the small squares) and buffers for driving global instruction and clock lines. The remaining outer ring of circuitry is dedicated to the 40 wire-bond pads. This circuitry uses 1.75 mm2 or 43.5 % of the chip's total area. It is interesting to note that the core smart pixel circuitry contains processing logic and 100 optical data I/O channels in just a bit more VLSI real estate.
| This is a photo of an individual smart pixel. Each smart pixel contains 182 transistors functioning as a 3-bit processing element that can optically detect and/or transmit a single data bit on each clock cycle. The circuitry was fabricated with Hewlett-Packard's 0.8 micron CMOS process. Two diodes (appearing as blue-gray rectangles in the upper portion of the pixel) operate as detectors to receive a dual-rail intensity encoded optical signal. The two diodes in the lower half of the pixel operate as modulators to transmit a dual-rail encode optical signal. Each pixel is 125 by 250 microns in area. The smart pixel operation is based on binary image algebra (BIA)[2] which breaks down complex data manipulation algorithms into three basic operations: complement (logical NOT), union (logical OR) and dilation. The smart pixel array operates as mesh connected single-instruction multiple-data (SIMD) processor, efficiently executing morphological image processing and other 'data-level' parallel algorithms. Since their are no global electronic interconnections the SPARCL architecture can operate at high clock rates. The SPARCL clock rate was simulated at over 100 MHz and has been tested at 90 MHz. |  |
We have constructed a demonstration system which interconnects up to three SPARCL chips in a 2D pipelined processing array. Data flows uni-directionally through the SPARCL pipeline on a 5 x 10 array of digital optical free space channels. The first SPARCL chip acts as the input to the pipeline by converting electronic column parallel data to optical 2D parallel data. The intermediate SPARCLs perform SIMD data processing and the final SPARCL converts the data back to 1D electrical form. The system is packaged on a 10" x 14" slotted baseplate housing polarization sensitive and diffractive optical components. A central controlling computer sends instructions to the SPARCL chips to perform data processing routines. The optical components used for this experiment are commercial-off-the-shelf products, except for custom designed diffractive optical elements (DOEs) for spot array generation.
We have run an extensive variety of image and video processing routines on the SPARCL system for testing and demonstrational purposes.
