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“Digital Image Processing on VLSI”
by Bing J. Sheu and Oscal T.-C. Chen
August 1991
An efficient processing element for data/image processing has been designed. Detailed communication networks, instruction sets and circuit blocks are created for ring-connected and mesh-connected systolic arrays for the retrieving and learning phases of the neural network operations. 800 processing elements can be implemented in 3.75 cm x 3.75 cm chip by using the 0.5 mm CMOS technology from TRW, Inc. This digital neuroprocessor can also be extended to support fuzzy logic inference.