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“S-CMOS: A Robust Deep-Submicron CMOS Transistor Model For Very Low-Power High-Frequency VLSI Application”
by Yoondong Park
April 1999
A robust deep-submicron Short-Channel MOS transistor model (S-CMOS) is developed. All operation region of MOSFET can be simulated with unified expression of S-CMOS including the triode, saturation, subthreshold, weak and strong inversion regions. The drift and diffusion currents merged into one simple unified current expression by implementing the sigmoid and exponential interpolation functions. The effective mobility expression includes the effects of lateral and vertical electric fields in the channel efficient degradation factor which simplifies the expression and reduce the computation time. Temperature dependency on threshold voltage and effective mobility was investigated and efficient model was developed. Simplified noise model was developed and simulated to implement the behavior of the noise in MOSFET devices. The unified drain current and terminal charge expressions in all regions of operation, which provides a highly continuous behavior for the conductances and capacitances are developed and the robustness verified by simulating every mathematical components. The charge model uses the better formulation of conductance degradation coefficient to model the channel charge density and the unified expressions of charge densities are valid for all operation regions, including the accumulation region. Non-quasi-static capacitance analysis was developed for radio frequency application. To increase the capability of the model, a unified first-order non-quasi-static model and time constants for long-channel transistor and high frequency derived. The characteristics of time constants in all geometric region are simulated and analyzed for high frequency VLSI application. Efficient parameter extraction procedure was developed by using multiple-objective function which is able to include not only drain current but also conductance and transcoductance characteristic of the transistor and the extraction procedure of the S-CMOS model was implemented in MATLAB software. Simulation results agree well with measurement data of transistors from a 0.35mm technology of MOSIS Service. The S-CMOS model is implemented into SPICE3f3 from Berkley successfully in SUN Solaris 2.6. and the performances comparison of S-CMOS, MOS Level2, Level, BSIM1, and BSIM3v3 models in circuits simulation including folded cascode Op Amp, analog multiplier, comparator, 8-bit carry save adder, and 8-bitx8bit carry save multiplier is demonstrated. Efficient 8-bitx8bit divider design and simulation results are included.